The present invention relates to semiconductor devices, in particular to electrically erasable programmable read-only memories (EEPROM).
Conventional EEPROMs include a election device connected in series with a memory device. The selection device controls the flow of current to the memory device. The memory device has a floating gate positioned over the channel and the tunnel dielectric area on the drain, and a stacked control gate positioned over the floating gate. Programming the memory device is achieved by applying a suitable potential across the drain and the control gate of the memory device to cause charge carriers to tunnel through the tunnel dielectric from the floating gate to the drain. Erasing the memory device is achieved by applying a suitable potential across the control gate and the drain of the memory device to cause charge carriers to tunnel through the tunnel dielectric from the drain to the floating gate.
The tunnel dielectric area on he drain of the memory device can be defined using conventional photoengraving technology. The area required to accommodate the tunnel dielectric is normally relatively large due to the dimensional limitations and alignment tolerance of conventional photoengraving technology. Thus, the resolution of the photoengraving technique can place an upper bound on memory cell density.
The tunnel dielectric area on the drain of the memory device can be reduced significantly using a self-aligned tunnel dielectric area approach, as disclosed in U.S. Pat. Nos. 5,021,848 and 5,019,879. In this approach, the tunnel dielectric area is not defined by conventional photoengraving in the channel direction. Rather, photoengraving is used to define the floating gate and to align the floating gate to the channel in the direction perpendicular to the channel direction.
With the advance of trench isolation techniques, the separation between adjacent diffusion lines is no longer necessarily limited by electrical isolation requirements. Instead, the separation is limited by the requirement of aligning an extension of the gate to form an endcap on the field oxide, and by the minimum spacing between adjacent end caps due to the photolithographic limitation.
In conventional EEPROMs, the selection device in series with the memory device can be eliminated, as disclosed in U.S. Pat. No. 5,355,347, by using a bit line page programming technique. In this technique, the drains of all single transistor memory cells in a column are connected to a bit line, the control gates of all single transistor memory cells in a row are connected to a word line, and the sources of all memory cells in each sector are connected to a sector select line. The most optimized memory array layout according to this technique requires one contact opening for the metal bit line interconnection shared by two adjacent memory cells, and the area required for the contact opening occupies about 40% of total memory cell area.
Conventional semiconductor devices use oxide or nitride spacers at the gate edge in the source and the drain area to form lightly doped source-drain structures under the oxide or nitride spacers. Devices using such structures have the disadvantages of high series resistance and high body effect, disadvantages that cannot normally be reduced by the voltage applied to the gate.
The present invention provides an EEPROM memory device with a channel and floating gate self-aligned to field oxide in an isolation trench. An add-on floating gate forms both a self-aligned endcap on the field oxide and a self-aligned tunnel area on a buried drain. The present invention further provides a method of fabricating the same, as well as a proposed segmented bit line pate memory array architecture. The proposed architecture and the method of forming the self-aligned end cap allow increasing the storage density of the array.
The proposed EEPROM floating gate memory device has a floating gate disposed over the channel between the buried drain and the buried source and insulated from the channel by 200 xc3x85 to 1000 xc3x85 of gate oxide, an add-on floating gate shorted electrically to the floating gate and disposed over and insulated from the buried drain by 15 xc3x85 to 150 xc3x85 of tunnel dielectric, and a control gate disposed and insulated from the floating gate and the channel between the floating gate and the buried source. Both the bating gate and the channel underneath are self-aligned to and flanked by the field oxide in the trench along a direction perpendicular to the channel current flow. The add-on floating gate forms the self-aligned end cap on the field oxide. The proposed memory device allows a reduction in memory cell size.
This memory cell is suited for use in a proposed segmented bit line page memory array architecture with the common drain diffusion line and the common diffusion source line both in a Y-column direction, and with the, common control gate line in an X-row direction. The architecture uses a reduced number of contact openings, and allows the use of a smaller surface area per memory cell.
In the proposed segmented bit line page memory array architecture, the drains of 4 to 4096 of the proposed memory cells within the same column and the sources of 4 to 4096 proposed memory cells within the: adjacent column are commonly connected to a single sub-bit line. The sub-bit line is connected to a bit line in the Y-column direction through a segment select device with its gate connected to a segment select word line in the X-row direction. The control gates of all the proposed memory cells within the same row are connected to the same word line in the X-row direction.
The present invention further provides an improved method of fabricating a semiconductor device during the fabrication of the proposed EEPROM memory cell. In the preferred embodiment, the self-aligned end cap on the field oxide and the poly spacer over the drain area are formed at the same time, after the lightly doped source and drain and the hallow implanted areas are formed. The proposed method of device fabrication provides for device size reduction and added flexibility in drain engineering for deep sub-micron device technology. The lightly doped source and the drain under the polysilicon spacer electrically connected to the gate can reduce the body effect and the series resistance of the device when the voltage is applied to the gate of the device to conduct current in the channel.
The preferred fabrication method includes the steps of using an active area (or diffusion) mask to define photoresist patterns on a nitride layer deposited on a first polysilicon layer, which in turn is deposited on a first gate oxide on the semiconductor substrate. Then the nitride layer, the first polysilicon layer, and the first gate oxide layer outside of the photoresist patterns are etched away. The exposed semiconductor substrate is subjected to a semiconductor etch to form shallow trenches between the active area photoresist patterns. After removing the photoresist patterns, a thin oxide layer is grown. Then a thin layer of nitride is deposited and etched back in an anisotropic etch to keep the thin nitride layer at the side wall of the trenches and also at the side wall of the first polysilicon on first gate oxide patterns.
A thick field oxide is grown in the trenches to form the field isolation structures, since the remaining area is covered by the nitride and no field oxide can be grown. Thus, the first polysilicon layer patterns are self-aligned to the field oxide in the trenches. Then the nitride and the first poly patterns are etched into the first poly gates of the non-memory devices and the floating gates of the EEPROM memory cells, using the first gate pattern mask to define the gate area. A thin nitride layer is again deposited and etched away except at the side wall of the first polysilicon patterns. This side wall nitride prevents the side wall of the first polysilicon patterns from growing oxide during the tunnel oxidation.
In the EEPROM memory cell areas, the buried drain areas are defined, the oxide in the buried drain areas is etched off, and arsenic and/or phosphorus are implanted to form buried drain for the EEPROM memory cells. A thin tunnel oxide is grown in the buried drain areas.
The next several steps are for the source drain engineering of the semiconductor devices. The source and the drain area of any N-channel devices are defined. The N-channel source and drain areas are then doped with a deeper boron anti-punch-through hallow implant, and a shallower light drain implant at slightly heavier phosphorus or arsenic doses. The source and drain areas of any P-channel devices are then defined. The P-channel source and drain area are doped with a deeper phosphorus anti-punch-through hallow implant, and a shallower light drain implant at slightly heavier BF2 dose. The above-described drain engineering allows fabricating short-channel-length devices with relatively heavier anti-punch-through implant doses, while suppressing the body effect of the devices because of the shallow light conductive drain at the surface channel.
After the formation of the buried drain for the EEPROM memory cells and after the drain engineering steps for the semiconductor devices, all nitride at the side wall of the first polysilicon gate is removed. The add-on polysilicon layer is deposited right afterward, in intimate contact with the side wall of the first polysilicon gate. Then, an add-on polysilicon pattern mask is used to define inter-connection patterns for the first polysilicon gates. The add-on polysilicon patterns are smaller than the first polysilicon gate patterns of the semiconductor devices such that the gate edges at the source and the drain areas are at the outside of the add-on polysilicon patterns. The first polysilicon floating gate areas of the EEPROM memory cells are not overlapped by the add-on polysilicon patterns.
The add-on polysilicon outside of the add-on polysilicon patterns is then etched back in an anisotropic etch such that the poly spacer is formed around the side wall of the first polysilicon floating gate patterns of the EEPROM memory cells. The poly spacer is also formed at the side wall of the first polysilicon gate patterns of the semiconductor devices outside of the add-on polysilicon patterns. The poly spacer on the field oxide attached to the first polysilicon gate forms the self-aligned end cap of the first polysilicon gate. The poly spacer attached to the first polysilicon gate in the active areas of the semiconductor devices becomes the self-aligned source drain overlap on the lightly doped source drain areas. The poly spacer attached to the first polysilicon floating gate over the buried drain areas of EEPROM memory cell forms the tunnel oxide areas of the EEPROM memory cell, while the poly spacer attached to the first polysilicon floating gate over the field oxide areas of EEPROM memory cell forms the self-aligned end cap of the first polysilicon floating gate.
A high voltage source drain implant window is then formed and implanted to form a high voltage source drain junction of the EEPROM memory cells and semiconductor devices. This method of simultaneously forming the small self-aligned source drain overlap area and the self-aligned end cap of semiconductor devices, as well as forming the self-aligned tunnel oxide area and the self-aligned end cap of the first polysilicon floating gate of EEPROM memory cell at the same time is incorporated in the preferred embodiment of the EEPROM in the trench isolated fabrication process.